Tips for power aware synthesis with RTL compiler by using dynamic switching activities from a VCD file.
The testbench must include the following lines to get all the lower-level signals listed on the VCD
$dumpfile ("test.vcd.gz");
$dumpvars (0, testbench.module_tb);
Synthesis script
set_attr lp_power_analysis_effort medium / read_vcd test.rtl.vcd.gz -vcd_module $design
# Build detailed power models for more accurate RTL power analysis
build_rtl_power_models -clean_up_netlist -clock_gating_logic report power -rtl_cross_reference -detail
Leakage power optimization
set_attr max_leakage_power 0.0 /designs/$design
Dynamic power optimization
set_attr max_dynamic_power 0.0 /designs/$design set_attr lp_power_optimization_weight 0.75 /designs/$design
More activity details can be found on:
rc:/> get_attr -h lp*default* *