RTL resource estimation and packing density

It is not the first time I was caught with Xilinx’s report on resource usage by hierarchy.

By default, Xilinx’s toolchain has itsĀ CLB Pack Factor Percentage defaulted to 100% (minimum packing density). Which in other words means that it will relax the constraints on how many device resources are allocated. Thus during the map phase, the registers and LUTs are not tightly packed into slices. This explains the mismatch between the resource usage report and the RTL resource estimation.

The CLB Pack Factor percentage can be changed via the -c argument on MAP.

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