Clock concurrent optimization

Since Cadence added Azuro’s ccopt by default in SOC Encounter, I think it is time to look deeper in this clock concurrent optimization. The latter was initiated by a company called Azuro which was then acquired by Cadence in July 2012. Clock concurrent optimization merges clock tree synthesis (CTS) with physical optimization, simultaneously building clocks […]

Why use path_adjust ?

path_adjust is used to either relax or tighten the timing constraints (even though defined by path_delay). e.g to relax the constraints by 100ps rc:>/ path_adjust -from [all_inputs] -to [all_outputs] -delay 100 -name pa_i2o e.g to tighten the constraints by 100ps rc:>/ path_adjust -from [all_inputs] -to $all_registers -delay 100 -name pa_i2r path_adjust is thus use to […]

database access with dbGet / dbSet

Found this old blog post “A dbGet Code Example” on the Cadence Digital Implementation useful. She described how to place power switch cells using dbGet and dbSet. It appears that dbGet and dbSet will be my go-to commands on EDI. I found out that using dbGet.selected.?? could list out not only the values but also […]

#SNUG25 and 14LPP process

Some highlights from Samsung during #SNUG Silicon Valley 2015 which I deemed interesting: 14LPP Process: 30 tapeouts since 2012, 6 product tapeouts in 2014. 28LPP 9T 15% lower pwr versus 12T. 14LPP 9T 1/3 lower. Benefits over 14LPP over 28LPP: 67% speedup / 59% less power / 45% less area Samsung and GlobalFoundries are collaborating […]

2015 ASIC respin trends by Wilson research

This year’s Wilson research from @mentor_graphics claims that at least a respin is required. However it does not yet state whether it is a planned respin or a bug-fix respin. Wilson research from @mentor_graphics says most #ASIC chips need at least one respin — testandverif (@testandverif) February 5, 2015