Since Cadence added Azuro’s ccopt by default in SOC Encounter, I think it is time to look deeper in this clock concurrent optimization. The latter was initiated by a company called Azuro which was then acquired by Cadence in July 2012.
Clock concurrent optimization merges clock tree synthesis (CTS) with physical optimization, simultaneously building clocks and optimizing logic delays based directly on a propagated clocks model of timing. Thus, the clock tree synthesis (CTS) becomes timing-driven and tightly coupled with placement and logic sizing. This is different from traditional techniques of sequential optimization and useful skew.
CTS is done by combining the benefits of pre-route layer-aware optimization and useful skewing.
Buffer insertion is not only done to just reduce the skew but also to do time borrowing and to improve the overall speed of the design.
What is the benefits of using CCopt ?
- Increased chip speed or reduced chip area and power
- Reduced IR drop
path_adjust is used to either relax or tighten the timing constraints (even though defined by path_delay).
e.g to relax the constraints by 100ps
rc:>/ path_adjust -from [all_inputs] -to [all_outputs] -delay 100 -name pa_i2o
e.g to tighten the constraints by 100ps
rc:>/ path_adjust -from [all_inputs] -to $all_registers -delay 100 -name pa_i2r
path_adjust is thus use to guide RTL Compiler to concentrate and focus on register to register timing instead of optimizing inputs to output paths.
When such path_adjust exceptions are created there are located at
“relative C threshold” and “total C threshold” in RC extraction are set by
Found this old blog post “A dbGet Code Example” on the Cadence Digital Implementation useful. She described how to place power switch cells using
It appears that
dbSet will be my go-to commands on EDI.
I found out that using
dbGet.selected.?? could list out not only the values but also the attributes of the selected objects. Thus, making easier to script
Some highlights from Samsung during #SNUG Silicon Valley 2015 which I deemed interesting:
- 14LPP Process: 30 tapeouts since 2012, 6 product tapeouts in 2014.
- 28LPP 9T 15% lower pwr versus 12T.
- 14LPP 9T 1/3 lower.
- Benefits over 14LPP over 28LPP: 67% speedup / 59% less power / 45% less area
Samsung and GlobalFoundries are collaborating on the 14nm process. The 14LPP process technology is a higher performance version over LPE, planned for early 2015.
This year’s Wilson research from @mentor_graphics claims that at least a respin is required. However it does not yet state whether it is a planned respin or a bug-fix respin.
Wilson research from @mentor_graphics says most #ASIC chips need at least one respin
— testandverif (@testandverif) February 5, 2015
In short, a metal gate rather than a polysilicon gate.
- Reduces gate leakage
- Increases transistor capacitances
- Improves the dielectric constant
- Manufacturing methods: Gate first, Gate Last
In SOC encounter(EDI), the command “all_analysis_views” gives all the views defined in viewDefinitions file.
To report active analysis views:
report_analysis_views -type active
To get all active setup/hold analysis views :