test or value with args

User defined arguments can be invoked with a verilog simulator. They can be used to simplify the design of models.

$test$plusargs is a system function which checks whether a “plus” option was used when simulation was invoked. e.g
$test$plusargs ("mem_preload"))


$ iverilog +mem_preload
$value$plusargs is a system function which assigns a value to the specified argument.
if ($value$plusargs ("TESTNAME=%S", testname)) is

iverilog +TESTNAME=example

Verilog: Bit slicing without constant

A dynamic slicing like the one described below will fail.

$display ("%x",temp[((i+1)*8):i*8]);

 Range must be bounded by constant expressions.

In Verilog 2005 syntax, this operation can be carried without contants by:

$display ("%x",temp[(i*8) +:8]);

8 is the width of the slice and will be added to i every iteration through the loop.

Power aware synthesis

Tips for power aware synthesis with RTL compiler by using dynamic switching activities from a VCD file.

The testbench must include the following lines  to get all the lower-level signals listed on the VCD

$dumpfile ("test.vcd.gz");
$dumpvars (0, testbench.module_tb);

Synthesis script

set_attr lp_power_analysis_effort medium /
read_vcd test.rtl.vcd.gz -vcd_module $design

# Build detailed power models for more accurate RTL power analysis

build_rtl_power_models -clean_up_netlist -clock_gating_logic
report power -rtl_cross_reference -detail

Leakage power optimization

set_attr max_leakage_power 0.0 /designs/$design

Dynamic power optimization

set_attr max_dynamic_power 0.0 /designs/$design
set_attr lp_power_optimization_weight 0.75 /designs/$design

More activity details can be found on:

rc:/> get_attr -h lp*default* *

soft error rate

In life critical application, customers like to have a grip on Single Event Effects (SEEs). These may cause unexpected data corruption due to radiation-induced failures.

SEEs are influenced by design, technology process and the system application.

[FEL]: archimedes 2.0.0 stable release

Archimedes, the 2D Quantum Monte Carlo simulator for semiconductor devices, has been updated on both Fedora and EPEL testing repositories.

Since last FEL release, archimedes entails the following changes:

  • The material parameters have been checked and modified
  • Benchmark tests were carried out to check the validity of the framework
  • Scattering phonons can be set to ON or OFF
  • Support for Full band approach was implemented
  • Parabolic, Kane and Full bank verified
  • Full band parameters supports for all materials
  • Initial implementation of FEM for Poisson
  • Quantum Effective Potential modified
  • Bohm Potential Model was implemented
  • Calibrated Bohm Potential Model was implemented
  • Density Gradient corrected and tested
  • Full effective potential model was implemented


FEL at DVClub Bristol, 20 Sep 2010

It is a pleasure to announce Free Electronic Lab and open source EDA is the topic of the DVClub Bristol meeting, 20 September 2010, at 11:30-2PM WEST/BST.

The talks will be 12-2PM (7-9AM EDT) via

  • web conference
  • in Bristol, England (Infineon, Great Western Court, Hunts Ground Road, Stoke Gifford, BS34 8HP)
  • Cambridge, England (The ARM office in Cambridge (110 Fulbourn Road, Cambridge, CB1 9NJ)
  • and Eindhoven, Netherlands.

The presentations are:

  • “Verilator; fast, free, but for me?”, by Wilson Snyder, developer of Verilator.
  • “Architecture For Massively Parallel HDL Simulations”, by Rich Porter from Art of Silicon.
  • “Free Electronic Lab: Hardware engineering made easy”, by Chitlesh Goorah, Digital Design Engineer, ON Semiconductor and developer of Free Electronic Lab.
  • “Processor verification using open source tools and the GCC regression test suite: A case study”, by Dr. Jeremy Bennett, founder and CEO of Embecosm.

We hope to see you (virtually) there. For details and to register, follow these guidelines.

This event is sponsored by ARM, Infineon, the NMI and TVS.

A freeware GLADE as an IC layout editor

It’s the first time, I’m writing about a freeware. But even though it is not opensource, this freeware does have interesting features which Toped developers are working on for Toped.

Glade is capable of reading GDS2, OASIS, LEF and DEF. Some of its features are;

  • Fast, hardware accelerated OpenGL graphics;
  • Import/Export GDS2, OASIS, DXF, LEF, DEF and Verilog;
  • Import Cadence display.drf and techfiles directly;
  • Edit and display hierarchy from 0 to an unlimited number of levels;
  • Create instance, label, rectangle, path, polygon, via, pin commands with interactive display during enter;
  • Layer select window for setting layer visibility/selectability, current layer, choosing layer colour and transparency, fill pattern, line style/width and setting layer names;
  • …and many others!

Since Glade being just a freeware and not opensource, it will not be available under the Free Electronic Lab(FEL) umbrella, the user is ought to download it from the developer’s website and execute the following commands manually.

[sourcecode language=”bash”]
$ export GLADE_HOME=`pwd`
$ export PATH="$PATH:$GLADE_HOME/bin"

Since Glade was not compiled under a FEL compatible repository, it crashes frequently. In either case, I would also recommend FEL users to use toped 
[sourcecode language=”bash”]# yum install toped[/sourcecode]
or magic
[sourcecode language=”bash”]# yum install magic[/sourcecode]
as they are tested and deeply rooted into FEL’s proposed design flows.

Floorplanning with Magic, how hard can that be ?

Alliance VLSI development cycle has stalled and there are many software compatibility issues that need to be solved before getting a proper (one that can meet the industry’s needs) digital backend flow with opensource software. Herb which was meant as a clone for Alliance VLSI will not be stable enough at the end of this year, nor I would expect some Mixed-Signal designs from it.

Since it won’t be TCL based, I doubt I would even use Herb myself. Hence, I’m investigating further on what should be done before one can design a mixed signal chip with the industry’s requirements.

Magic VLSI is fairly analog oriented, it is TCL based and it is lambda based. Since it is TCL based, it deserves credits. But being lambda based it makes it hard to go beyond 90nm process node with it since it won’t be accurate enough. Surely a timing correlation would prove this.

Magic’s 2 grid cells normally represent the length of the transistor. However, macro models of SRAM/ROM available in the LEF format include decimal points to reflect the position of different metal layers and vias. This is a major drawback with Magic VLSI.

Achieving digital implementation with Magic would certainly require new techniques about  how to use magic itself and how metrics (resistances, capacitances, switching activities,..) are extracted.

I started today with a case scenario: try to get a simple floorplan setup with some macro models. Nigel Nordsworth has kindly forwarded some Macro models. He is FEL’s test contributor for more than a year now. As mentioned above, LEF files might include X and Y positions with 3 decimal points in microns. Hence, to load the macro models, these X and Y positions should be multiplied by 1000 and thereby converting them into the nanometer scale.

Our current possible solution would be to use a Magic’s grid cell to represent 1 nm². This is not how one would normally use Magic. The complexity slope rises as all the tech files should be revisited and possibly be project dependent. Being project dependent, the solution would not be useful for the normal user. But once we can get a proper TCL package with can help us rotate the macro models and one of the 3 internal routers of magic can actually do some power routings (VDD and GND), we will present our solution for standardization.

[sourcecode language=”bash”]
instance_name ""
foreach instance [ cellname list instances ] {
if { $instance == $element_name } {
set instance_name $element_name

select cell $instance_name
instance celldef $instance_name

regsub {.} $xl {} xl
regsub {.} $yl {} yl
move to $xl $yl

puts "Info: Moved the following selected Macro to ($xl,$yl)"

Using the above TCL commands just to move around the macro model I believe that a digital implementation should be feasible with Magic VLSI. But some intelligent mechanisms should be investigated about the timing and power correlations. As I wrote in the past, coupled with IRSIM we can even estimate leakage power out of the design during standby mode.

It should be exciting to design low power and low voltage designs.

[FEL]: Standard Cell characterisation – part two

Xcircuit 3.6 series brings on technology library support, which enables anyone to maintain customed analog or digital IPs, independent of the schematic design. This powerful feature, coupled with ngspice, helps the designer to maintain their spice commands within the testbench schematic. It will automatically extracts the spice netlists with the subcircuits included, then from the tcl console simulate the design.

However this was not working out of the box and the user needed to patch ngspice. Since ngspice rework 17, Fedora’s ngspice was patched accordingly. But with ngspice rework 19, it broke. This week Holger Volgt improved the patch and merge it to ngspice cvs branch.

This blog post will briefly show a testcase about how to invoke ngspice within Xcircuit directly.

Launch Xcircuit and load your design. Here, I’ll take a simple invertor as example. Then launch the Tcl console from the file menu and type

::xcircuit::spice start

If you encounter this error, you are certainly using an older version of ngspice.

There is already an update in the fedora repositories which fixes this issue.

On the screenshot below, you can see the invertor in a test situation alongside spice commands for the simulation. Hence there is no need to maintain extra file or makefile to launch SPICE simulation. Everything is launched and saved by Xcircuit in a postscript format.

::xcircuit::spice start

(extracts the spice netlist and sets the initial condiction.)

::xcircuit::spice run

(executes the simulation)

::xcircuit::spice send “plot v(Vin) v(Vout)”

(sends the plot command to ngspice and displays the plot)

Arun SAG has recently filed a package review request for emacs-spice-mode. Once approved and pushed to Fedora repositories, you can execute spice simulations within emacs as well.