test or value with args

User defined arguments can be invoked with a verilog simulator. They can be used to simplify the design of models. $test$plusargs is a system function which checks whether a “plus” option was used when simulation was invoked. e.g $test$plusargs (“mem_preload”)) Usage: $ iverilog +mem_preload $value$plusargs is a system function which assigns a value to the […]

Verilog: Bit slicing without constant

A dynamic slicing like the one described below will fail. $display (“%x”,temp[((i+1)*8):i*8]);  Range must be bounded by constant expressions. In Verilog 2005 syntax, this operation can be carried without contants by: $display (“%x”,temp[(i*8) +:8]); 8 is the width of the slice and will be added to i every iteration through the loop.

Power aware synthesis

Tips for power aware synthesis with RTL compiler by using dynamic switching activities from a VCD file. The testbench must include the following lines  to get all the lower-level signals listed on the VCD $dumpfile (“test.vcd.gz”); $dumpvars (0, testbench.module_tb); Synthesis script set_attr lp_power_analysis_effort medium / read_vcd test.rtl.vcd.gz -vcd_module $design # Build detailed power models for […]

[FEL]: archimedes 2.0.0 stable release

Archimedes, the 2D Quantum Monte Carlo simulator for semiconductor devices, has been updated on both Fedora and EPEL testing repositories. Since last FEL release, archimedes entails the following changes: The material parameters have been checked and modified Benchmark tests were carried out to check the validity of the framework Scattering phonons can be set to […]

FEL at DVClub Bristol, 20 Sep 2010

It is a pleasure to announce Free Electronic Lab and open source EDA is the topic of the DVClub Bristol meeting, 20 September 2010, at 11:30-2PM WEST/BST. The talks will be 12-2PM (7-9AM EDT) via web conference in Bristol, England (Infineon, Great Western Court, Hunts Ground Road, Stoke Gifford, BS34 8HP) Cambridge, England (The ARM […]

A freeware GLADE as an IC layout editor

It’s the first time, I’m writing about a freeware. But even though it is not opensource, this freeware does have interesting features which Toped developers are working on for Toped. Glade is capable of reading GDS2, OASIS, LEF and DEF. Some of its features are; Fast, hardware accelerated OpenGL graphics; Import/Export GDS2, OASIS, DXF, LEF, […]

Floorplanning with Magic, how hard can that be ?

Alliance VLSI development cycle has stalled and there are many software compatibility issues that need to be solved before getting a proper (one that can meet the industry’s needs) digital backend flow with opensource software. Herb which was meant as a clone for Alliance VLSI will not be stable enough at the end of this […]

[FEL]: Standard Cell characterisation – part two

Xcircuit 3.6 series brings on technology library support, which enables anyone to maintain customed analog or digital IPs, independent of the schematic design. This powerful feature, coupled with ngspice, helps the designer to maintain their spice commands within the testbench schematic. It will automatically extracts the spice netlists with the subcircuits included, then from the […]