[FEL]: Standard Cell characterisation – part one

Both xcircuit and ngspice has been updated for Fedora/EPEL-5 last week with some key features to boost productivity for standard cell characterisation. I’ll explain briefly in two blog posts, thus this one is the first post. Last week, Fedora users have updated their ngspice rework 19 to rework 20 (20-1.fc12), with the following key highlights […]

Setup a customed RCS command commitdate.

(same can be applied to systemverilog files) How to set up a customed RCS command commitdate with git: $ git init $ echo ‘*.vhd ident’ >> .gitattributes $ echo ‘*.vhd filter=rcs-keyword’ >> .gitattributes $ git config filter.rcs-keyword.clean ‘perl -pe “s/$commitdate[^$]*$/$commitdate$/”‘ $ git config filter.rcs-keyword.smudge ‘perl -pe “s/$commitdate[^$]*$/$commitdate: `date`$/”‘ Open a vhdl design file in the […]

[FEL]: Power Estimation at transistor Level

One of the least advertised features of IRSIM is its ability to quickly estimate power of large VLSI circuits from gate level netlists (.sim). To install IRSIM on Fedora (default on Fedora Electronic Lab): # yum install irsim This estimation is based on the ‘three-level quantization scheme’, where the voltage can assume 3 values (GND, […]

[FEL]: Status of Electric VLSI on Fedora

Fedora 11 stable repositories provides Electric VLSI 8.08. Upstream released a new release version 8.09 which won’t be pushed to Fedora stable repositories. Please note that because most of the Fedora electric userbase (I’m referring to mostly universities in France and Japan) use third party plugins that due to the licensing incompatibilities wih Fedora, FEL […]

A junior ASIC Guy Visits An FPGA World

The title of this blog post was copied from Harry Gries’s blog post An ASIC Guy Visits An FPGA World and reflects my thoughts as a junior. Harry’s observations are oriented towards the “raw” design methodology proposed by the FPGA design tools vendors. Coming from the ASIC environment, we are heavily design methodology oriented and […]

EDA: standard cells for chip design

A standard cell is group of transistor and interconnect structures, which provides a boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or latch). All CAD tools for chip design (whether proprietary or open source) require standard cell libraries. These standard cell libraries contain primitive cells required for digital design. […]