[FEL]: Standard Cell characterisation – part one

Both xcircuit and ngspice has been updated for Fedora/EPEL-5 last week with some key features to boost productivity for standard cell characterisation. I’ll explain briefly in two blog posts, thus this one is the first post.

Last week, Fedora users have updated their ngspice rework 19 to rework 20 (20-1.fc12), with the following key highlights :

  • Updated BSIM4 code to BSIM 4.6.5 in accordance to this document.
  • Piecewise linear(PWL) functionality for B sources.
  • Support of 5-terminal bjt’s in subckt’s by prepending subckt name (similar things should be made for 5-7 terminal mos transistors, like soi models).
  • New measurement code, which is the most awaited feature for standard cell characterisation.

Currently the measurement code is still undocumented, so I hope this blog post will help ngspice users understand with their baby steps with ngspice’s .meas command. Though it follows the same syntax as HSpice, it still not yet complete. Hopefully the next ngspice releases will smooth the edges.

.meas command

Anyone who is characterising standard cells can now use .meas command and it surely helps to maintain an automatic flow.

For the sake of simplicity, I’ll cover a transient simulation as example, however one can also use it for voltage transfer characteristic of the cell.

.tran 0.1 18n uic

Define a parameter :

.param vp = 3.0v

Calculate maximum voltage of signal Vout from 4 ns to 10 ns

.meas tran vmax max v(Vout) from 4n to 10n

Calculate minimum voltage of signal Vout from 6 ns to 15 ns

.meas tran vmin min v(Vout) from 6n to 15n

Calculate the fall delay between the falling edge of the signal Vin and the falling edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_f trig v(Vin) val=’vp/2′ fall=1 targ v(Vout) val=’vp/2′ fall=1

Calculate the rise delay between the rising edge of the signal Vin and the rising edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_r trig v(Vin) val=’vp/2′ rise=1 targ v(Vout) val=’vp/2′ rise=1

These are the basic .meas commands which can be extended for ripple calculation and many of the user’s needs. The above image, created with ‘dia’, describes visually those commands.

Upon simulation, ngspice will output :

Transient Analysis

vmax                =  3.300000e+00 at=  1.000000e-08

vmin                =  2.589696e-04 at=  1.480631e-08

delay_f           =  4.780022e-10 targ=  1.052800e-08 trig=  1.005000e-08

pdelay_r           =  2.980831e-10 targ=  5.448083e-09 trig=  5.150000e-09

More examples can be found about the .meas command with

$  rpm -qld ngspice-doc | grep meas

Setup a customed RCS command commitdate.

(same can be applied to systemverilog files)

How to set up a customed RCS command commitdate with git:

$ git init
$ echo '*.vhd ident' >> .gitattributes
$ echo '*.vhd filter=rcs-keyword' >> .gitattributes
$ git config filter.rcs-keyword.clean 'perl -pe 
$ git config filter.rcs-keyword.smudge 'perl -pe 
      "s/$commitdate[^$]*$/$commitdate: `date`$/"'

Open a vhdl design file in the project directory:

$ emacs testbench.vhd

Edit the header template to add the $commitdate$ keyword and add a header for the VHDL file.

Within emacs,

Alt-x git-status
a -- Add file
c -- commit file

Checkout from Git repository

$ git checkout -- testbench.vhd

[FEL]: Power Estimation at transistor Level

One of the least advertised features of IRSIM is its ability to quickly estimate power of large VLSI circuits from gate level netlists (.sim).

To install IRSIM on Fedora (default on Fedora Electronic Lab):

# yum install irsim

This estimation is based on the

  • ‘three-level quantization scheme’, where the voltage can assume 3 values (GND, VDD/2 and VDD). It is fairly more accurate than the ‘two-level rail-to-rail model’.
  • measurement of glitching power.
  • estimates reasonably close to those that can be derived by measuring currents with a SPICE simulator with an error of less than 20% and a speed up of about 500 times.
  • incremental power measurement.

[FEL]: Status of Electric VLSI on Fedora

Fedora 11 stable repositories provides Electric VLSI 8.08. Upstream released a new release version 8.09 which won’t be pushed to Fedora stable repositories.

Please note that because most of the Fedora electric userbase (I’m referring to mostly universities in France and Japan) use third party plugins that due to the licensing incompatibilities wih Fedora, FEL can not entail those plugins. That said, Fedora Electronic Lab team understands that releasing a new upstream version would break interoperability with the user’s plugins.

Hence new versions of electric will only make their way to the fedora updates-testing repository.

# yum install electric –enablerepo=updates-testing


Electric is one of the FEL packages which by Fedora user’ requests we are giving most of our attention.

A junior ASIC Guy Visits An FPGA World

The title of this blog post was copied from Harry Gries’s blog post An ASIC Guy Visits An FPGA World and reflects my thoughts as a junior.

Harry’s observations are oriented towards the “raw” design methodology proposed by the FPGA design tools vendors. Coming from the ASIC environment, we are heavily design methodology oriented and work hard to satisfy design tools. But in the FPGA environment, the design tools provide an even more automated work flow from frontend to backend. Physical design sometimes (depending on the size of the design) seems to take a few minutes. I have seen people even skip the entire the physical design, unless there is a violation somewhere.

I had a few FPGA projects to handoff and though they were for some different medium-sized companies, sometimes I felt that project managers and reviewers were not serious enough like in ASIC environment. I got a few remarks for my VHDL designs which sometimes coming from a senior FPGA designer shocked me. It is true as well that FPGA design was not their prime development base.

One of those remarks which till now I have not really understood the reason between it and why my reasoning was not valid. It concerned my FSMs. They had “next-state” decoding and “output” decoding into two separate VHDL processes. My reasoning which Altera’s appplication notes implies will restrict the synthesis tool from sharing resources with other blocks. The remark I got, during a code review, was “I never seen that in my 12 years career, clean this”. I am still eager to know what advantage will my design have while combining these two processes.

I also got the most chaotic code review experience with other FPGA designers. VHDL code review was left incomplete from my point of view and discarded parts of code review with respect to switching rates, power, … due to lack of time. I was expecting a thorough code review for an optimal the sign-off and hand-off like I used to see with ASIC design teams.

I’m sure this is not true in every FPGA design team. What I was to say here is that during the excursion to the FPGA world, the strict discipline routine one has in ASIC environment just fades away. How quickly? I think it depends on the FPGA design team. I could even feel how disconnected the small companies are from the EDA vendors. However, I wish to get myself involved with a “real” high-performance FPGA based design team to see how discipline they are 🙂

While these are issues I personally encountered, I am trying to get Fedora Electronic Lab enough collaborative solutions so that small companies can at least have a decent code review, project hand-off and make FPGA designers happy.

FEL: linsmith and electric 8.08

The Smith Charting program, linsmith, will soon land on fedora repositories as new package.

Electric 8.08 will hit fedora-updates repositories as well in the upcoming hours.

EDA: standard cells for chip design

A standard cell is group of transistor and interconnect structures, which provides a boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or latch). All CAD tools for chip design (whether proprietary or open source) require standard cell libraries. These standard cell libraries contain primitive cells required for digital design.

A fedora user will have some standard cell libraries from

  • the alliance package
  • the pharosc package
  • # yum install pharosc*

    Pharosc provides five new open source standard cell libraries, the vsclib, wsclib, vxlib, vgalib and rgalib. They have been drawn with the Graal software from Alliance, part of an extensive open source software suite for designing integrated circuits with a standard cell design methodology.

    The libraries have been characterized in a generic 0.13µm technology, compatible with most foundry rules. Pharosc is the result of a book that Graham Petley is writing, The Art of Standard Cell Library Design.

    Among the standard cells from pharosc there are many scripts to provide interoperability between magic, alliance and xcircuit as well as scripts to allow one to update actual cells or create his/her own cells (pharosc-devel). There are more than 500 spice decks which can be simulated with either gnucap or ngspice.

    Each single component in any standard cell library comes with a well documentation html manual.
    The latter entails schematics, layouts and several parameters for spice simulation. The transistor schematics for the libraries have been drawn with Xcircuit, which uses Postscript as its native file format.

    Pharosc entails Alliance’s sxlib which has been characterised in 0.13µm using the same methodology and converted to the same 0.13µm layout rules. There is also an ssxlib which is the Alliance sxlib converted with a script from 1µm to 2µm layout and adjusted to obey DSM layout rules. The adjustments change the timing slightly.