Quartus 17.0 Prime install on Fedora 26

After installling Quartus on a x86_64 fedora 26, I fell upon the lib12.so.0 error.

$ quartus

quartus: error while loading shared libraries: libpng12.so.0: cannot open shared object file: No such file or directory

The simple solution is

$ sudo dnf install libpng12-devel.i686

Unfortunately I was not unable to program the bitstream on the fpga, thus I started debugging the jtag connection:

$ dmesg | tail
$ lsusb | grep Altera

$ gedit /etc/udev/rules.d/51-usbblaster.rules &

Paste the following on the file:

# For Altera USB-Blaster permissions.
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6001", MODE="0666"

$ sudo mkdir /etc/jtagd
$ sudo cp /home/chitlesh/intelFPGA_lite/17.0/quartus/linux64/pgm_parts.txt /etc/jtagd/jtagd.pgm_parts.txt
$ jtagd --foreground --debug

JTAG daemon started
Using config file /etc/jtagd/jtagd.conf
Remote JTAG permitted when password set
No USB device change detection because libudev.so.0 not found
Can't bind to TCP port 1309 - exiting

It appears I was missing libudev.so.0

$ sudo dnf install systemd-devel.i686
$ sudo killall -9 jtagd
$ jtagconfig

1) USB-Blaster variant [2-1.2]
Unable to lock chain - Insufficient port permissions

$ sudo udevadm control --reload
$ sudo killall -9 jtagd
$ sudo /home/chitlesh/intelFPGA_lite/17.0/quartus/bin/jtagconfig

1) USB-Blaster [2-1.2]
020F30DD 10CL025(Y|Z)/EP3C25/EP4CE22

Furthermore, since I imported the nios software projects from windows, I had to delete the .metadata directory to avoid strange incompatibility errors while compiling nios software projects.


Modelsim Intel-Altera 10.5c on Fedora26

This blog post is about how to run Modelsim Intel-Altera 10.5c on Fedora 26 (4.12.13-300.fc26.x86_64) after its installation. Modelsim Intel-Altera 10.5c comes with intelFPGA_pro 17.0.

First install the 32-bit libraries.

$ sudo dnf install glibc.i686 zlib.i686 bzip2-libs.i686 libXft.i686 libXext.i686 ncurses-compat-libs.i686

Download the freetype of el7 from here and copy the so files to modelsim’s internal directory.

$ rpm2cpio freetype-2.4.11-9.el7.i686.rpm | cpio -idmv
$ cp usr/lib/libfreetype.so.6* intelFPGA_pro/17.0/modelsim_ase/lib/

Add the following lines to the .bashrc :

$ export PATH=$PATH:~/intelFPGA_pro/17.0/modelsim_ase/bin
$ alias vsim="LD_PRELOAD=\"/home/$USER/intelFPGA_pro/17.0/modelsim_ase/lib/libfreetype.so.6\" vsim"

If vsim is launched at this time, you will get the following error:

Error: cannot find “/home/chitlesh/intelFPGA_pro/17.0/modelsim_ase/bin/../linux_rh60/vsim”

This error occurs because the intelFPGA’s vsim script has not considered linux kernels 4.*.

[chitlesh@localhost ~]$ uname -r

Add this following line on line 210 of bin/vsim.

4.[1-9][0-9]*) vco="linux" ;;

Below line 50 dir=`dirname "$arg0"`, add

export LD_LIBRARY_PATH=${dir}/lib

If DPI-C is not required, rename all the gcc directories into _gcc and use +UVM_NO_DPI.

That’s it.


If you find this blog post useful, please do leave a comment below to let me know if you have successfully run Altera Modelsim on Fedora.

RTL resource estimation and packing density

It is not the first time I was caught with Xilinx’s report on resource usage by hierarchy.

By default, Xilinx’s toolchain has its CLB Pack Factor Percentage defaulted to 100% (minimum packing density). Which in other words means that it will relax the constraints on how many device resources are allocated. Thus during the map phase, the registers and LUTs are not tightly packed into slices. This explains the mismatch between the resource usage report and the RTL resource estimation.

The CLB Pack Factor percentage can be changed via the -c argument on MAP.

NIOS: alternative to IOWR

NIOS II programming is easy with the default include files and functions. An alternative to write to registers using simple C programming can be the following:


IOWR() uses the ‘stio’ instruction in order to bypass the data cache.

int *sensor_reg0 = (int)*SENSOR_BASE;
*(sensor_reg0) =0xAA;

SENSOR_BASE, which is an address in this example, should have its 31th bit set in order to bypass the data cache.

signaltap – signals in red

With signaltap, when the signal is highlighted in red, it is because the signal is invalid after analysis and elaboration.

It could be that the signal is not driving anything and got scrapped off.

Alternatively, the technology viewer might help to debug.

Quartus 13.1 on Fedora 20

Installing Altera Quartus on Fedora 20 64-bit:

$ ./setup.sh

You must have the 32-bit compatibility libraries installed for the Quartus II installer and software to operate properly.


# yum install glibc.i686 libXext.i386 libX11.i386 libXau.i386 libXdmcp.i386 freetype.i386 fontconfig.i386 expat.i386

Detecting Papilio – FPGA

Detecting the device :

$ ./papilio-prog -v -c

Could not access USB device 0403:6010.

If you receive this error message, then the user isn’t part of the plugdev group.

$ ./papilio-prog -v -c

Using built-in device list
JTAG chainpos: 0 Device IDCODE = 0x11c1a093    Desc: XC3S250E

ISC_Done       = 0
ISC_Enabled    = 0
House Cleaning = 1
DONE           = 0
USB transactions: Write 4 read 3 retries 6