uvm_dpi 32-bit requirements on Fedora 26

This morning I was trying to compile uvm’ s dpi plug on Fedora 26 and ended with the following error:

Model Technology ModelSim – Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017
vlog “+incdir+uvm-1.2/src” uvm-1.2/src/dpi/uvm_dpi.cc
** Warning: ** Warning: (vlog-7032) The 32-bit glibc RPM does not appear to be installed on this machine. Calls to gcc may fail.

— Compiling DPI/PLI C++ file uvm-1.2/src/dpi/uvm_dpi.cc
** Error: (vlog-70) Compilation of the C/C++ src files failed with the error messages given below.

In file included from /usr/include/features.h:434:0,
from /usr/include/bits/libc-header-start.h:33,
from /usr/include/stdlib.h:25,
from uvm-1.2/src/dpi/uvm_dpi.cc:33:
/usr/include/gnu/stubs.h:7:27: fatal error: gnu/stubs-32.h: No such file or directory
compilation terminated.

The solution is simply:

$ sudo dnf install glibc-devel.i686

Modelsim Intel-Altera 10.5c on Fedora26

This blog post is about how to run Modelsim Intel-Altera 10.5c on Fedora 26 (4.12.13-300.fc26.x86_64) after its installation. Modelsim Intel-Altera 10.5c comes with intelFPGA_pro 17.0.

First install the 32-bit libraries.

$ sudo dnf install glibc.i686 zlib.i686 bzip2-libs.i686 libXft.i686 libXext.i686 ncurses-compat-libs.i686

Download the freetype of el7 from here and copy the so files to modelsim’s internal directory.

$ rpm2cpio freetype-2.4.11-9.el7.i686.rpm | cpio -idmv
$ cp usr/lib/libfreetype.so.6* intelFPGA_pro/17.0/modelsim_ase/lib/

Add the following lines to the .bashrc :

$ export PATH=$PATH:~/intelFPGA_pro/17.0/modelsim_ase/bin
$ alias vsim="LD_PRELOAD=\"/home/$USER/intelFPGA_pro/17.0/modelsim_ase/lib/libfreetype.so.6\" vsim"

If vsim is launched at this time, you will get the following error:

Error: cannot find “/home/chitlesh/intelFPGA_pro/17.0/modelsim_ase/bin/../linux_rh60/vsim”

This error occurs because the intelFPGA’s vsim script has not considered linux kernels 4.*.

[chitlesh@localhost ~]$ uname -r

Add this following line on line 210 of bin/vsim.

4.[1-9][0-9]*) vco="linux" ;;

Below line 50 dir=`dirname "$arg0"`, add

export LD_LIBRARY_PATH=${dir}/lib

If DPI-C is not required, rename all the gcc directories into _gcc and use +UVM_NO_DPI.

That’s it.


If you find this blog post useful, please do leave a comment below to let me know if you have successfully run Altera Modelsim on Fedora.

Do not delete Questa’s Excel plugin installer

It caught me by surprise.

Questa’s Testplan Tracking Excel plugin installer requires the previously used installer during its update.

Unfortunately, it doesn’t even show which version of the installer was previously installed. Thus making hard to first find the correct version of the installed plugin and its installer, prior to the update.

Note to self:

Do no delete the installer of Questa’s Excel plugin!

Mismatch when merging UCDBs

$ vcover merge -strip 0 -totals -verbose 
merge.ucdb testplan.ucdb coverage.ucdb

** Error: (vcover-6823) Can’t read UCDB file testplan.ucdb, the database was generated by a more recent version of Questa, and this version 10.2b can’t read it.


$ sed -i "s|10030047|10020046|" testplan.ucdb

Mentor's webinar about FPGA Synthesis techniques

This morning I attended Mentor Graphics’s webinar about FPGA Synthesis, by Roger Do and Robert Jeffery.

Synthesis is a stage in the design flow that I personally give a lot of attention to the reports and the constraints. I am always excited about Synthesis. It is a moment that the designer and the synthesis tool share a bond. The webinar was fine and the key items covered were

  • Register retiming
  • Resource sharing
  • Physical-aware synthesis
  • Incremental synthesis
  • Interconnect delays

From my perspective, the webinar was not too FPGA oriented as the webinar’s title suggested but covered common elements that one will also encounter in ASIC design. I was hoping to learn more about extra features that a third-party EDA vendor might provide that the FPGA providers don’t.

At the end, I asked a question about how the TCL scripting commands/arguments. From my point of view, the more there are tools from different vendors in a design flow the more complex is to automate the flow by scripting. Hence I wanted to know more about how the learning curve is when scripting with a third-party synthesis tool for FPGA design. My question was taken as what are the benefits of scripting, but not how difficult would it be for learning different commands/arguments from different vendors which do more or less the same task.

However, I really enjoy the webinar and thank MentorGraphics for their bi-weekly webinars. I am looking forward for the next webinar about CDC (Clock Domain Crossing).

I also participated in their poll. One of the questions on the poll was about which vendor’s FPGA I am using. I am always impressed to see in such poll that 2/3 of the participants choose Xilinx’s FPGA over Altera’s FPGA. I have not yet understood the reason behind it. One of the reasons I would choose Altera’s FPGA is because their constraints are in the SDC format, whereas Xilinx uses its own. It reassures me about the certainty of the constraints I want to apply. Hence,this ensures a quicker prototyping for a junior ASIC guy like me who visits the FPGA world.

Thank you, Cadence and Mentor Graphics

Cadence and Mentor Graphics have both announced on the same day (4/12/2008) [1] [2]that Open Verification Methodology is available under the Apache 2 license.

While thousands of verification engineers are already using it, now if OVM gets into Fedora repositories, we will be providing industry-class verification tools for our FEL users. OVM is maintained by Cadence and Mentor Graphics.

Believe me or not, this is one step forward for the Fedora Electronic Users to meet interoperability. However, till now I haven’t seen an opensource systemverilog tool that supports it.

I have just submitted OVM for package review, while hoping to get OVM into Fedora repositories in the upcoming days.