How to install yosys on Fedora 26

Unlike my other posts in the past decade where I referred to install anything from a rpmbuild, today I just want to get the install done and move on.

Prequisites for the yosys installation:
$ sudo dnf install clang tcl-devel readline-devel libffi-devel mercurial iverilog

Yosys build:
$ git clone
$ cd yosys/
$ make
$ make test
$ sudo make install

Build the Z3 SMT solver
$ git clone
$ cd z3/
$ python scripts/
$ cd build/
$ make
$ sudo make install

$realtime in SV assertions

$realtime is the de-facto system function I use when writing SystemVerilog assertions. The limitation of $time lies in its 64-bit integer value.

$realtime enables SystemVerilog assertions to be re-used in gate-level simulations. I’m glad that Ben Cohen, the renowned SVA expert, agrees with me on this.

AlexOrr’s first 100 days in formal-land

This weekend, I caught up with a presentation from @AlexOrr of Broadcom in which he talks about his “first 100 days in formal-land”.

I wanted to read it for a very long time. After reading the slides offline, I felt that this presentation was worth attending in person.

Within those slides, one can feel his experience and his desire to share it with the Design And Verification Engineer (DAVE) community.

@AlexOrr’s presentation is from #JUG2015. Blog posts related to Jasper User Group 2015 can be found here.

There are two items from his presentation I was repeating for a long time to my peers: Assertions and Jenkins. It is good to hear someone else is emphasizing on them as well.


Below are some key takeaways from Alex’s presentation. They are not new. However, they should be reminded over and over again.

Assumptions become assertions in simulation.

Do I have to retest all the reset values over and over again ?

I assume he was hinting at UVM built-in sequence uvm_reg_hw_reset_seq.

Assertions more portable than dynamic tests.

Use assertions, path spoilers, monitors, and/or illegal_bins statements. As well as $past.

Leverage “SuperLint” apps such as X-Prop.


To exclude specific registers from being tested against the predefined UVM sequence uvm_reg_hw_reset_seq:

uvm_resource_db#(bit)::set({"REG::", m_env_cfg.dut_rm.rffe_testctrl_reg.get_full_name(), "*"}, "NO_REG_HW_RESET_TEST", 1, this);

reg_hw_reset_seq] Response queue overflow

Encountered the following error message today, while using the pre-defined UVM sequence uvm_reg_hw_reset_seq :

UVM_ERROR @ 84050000:[uvm_test_top.m_env.m_core_agent.m_core_sequencer.reg_hw_reset_seq] Response queue overflow, response was dropped

This occurred because the driver was sending a sequence response to the sequencer via the seq_item_port. The default size of the response queue between the sequence and driver is 8. When the queue is full, it loses the response and generates an error.

The latter can be masked with:

Active path during register read access

Stumbled into a data corruption during a register read.

The adapter’s bus2reg function is called twice during the transaction. This behaviour is correct as the uvm_sequence_items of both the monitor and the driver (REQ) are broadcasted. But the driver should provide the final data for the adapter to translate.


register read()’s active path: => sequencer => register adapter => driver => adapter => sequencer =>

Instead of duplicating the monitor’s logic to decode the protocol, I recommend to use an UVM configuration database to propagate the decoded data from the monitor to the driver.

Do not delete Questa’s Excel plugin installer

It caught me by surprise.

Questa’s Testplan Tracking Excel plugin installer requires the previously used installer during its update.

Unfortunately, it doesn’t even show which version of the installer was previously installed. Thus making hard to first find the correct version of the installed plugin and its installer, prior to the update.

Note to self:

Do no delete the installer of Questa’s Excel plugin!