Just noticed that Questa has a UVM register definition generator, vreguvm. $ vreguvm -autoinstance -block default_top_block -csvin myproject.csv -uvmversion 1.1 -uvmout registers_pkg_uvm.sv
On the quest to remove redundant code from my testbenches, $time was among the victims to be dropped from all SV call $fatal. Now I’m using $realtime instead of $time when writing SVAs. Take the following statement along with its output as example: $fatal(`ASSERT_LEVEL, “[%m]: Assertion property pp_ahb_readyout_resp failed @ time %0t”, $time); # […]
Some UVM related command line functions on questa: ‘call’ can be used to call any UVM SV function. ‘findregisters, fr’ can be used to find HDL registers for a UVM register model. ‘findsequences, fs’ can be used to find currently active sequences. ‘find insource’ searches through only compiled code to find the given matching string. […]
[START_SEQ] and [STARTING_SEQ] from the transcript got me intrigued: Why UVM’s verbose spits them out? [START_SEQ] is due to a sequence start on the sequencer, while [STARTING_SEQ]s are due to start of predefined UVM_REG sequences.
Came across this tweet: @PVCocotb @pmarriott @dave_59 @GordonMcGregor @luked80 http://t.co/Unis4VGGYZ registered. I'll get a placeholder web page up Real Soon. — Bryan Murdock (@bdmurdock) January 14, 2015 The website says: Freecellera Because requiring $7,500 or $25,000 USD a year per member seems counter to the stated goal, “to develop technology standards that are balanced, open, […]
Always raise the phase objection in the test (instead of in the sequence), prior to starting any sequence.
In blocking tasks, the producer calls the put method through a port. uvm_blocking_put_port #(type) producer_port; producer_port.put(item); The consumer provides an implementation of the put method and declares an export which can be connected to the port of the producer. uvm_blocking_put_imp #(type, consumer) consumer_export; function void put (type item); Connection on the top level component: m_producer.producer_port.connect […]
How to generate UVM testbench code from Doulos‘s easier-uvm script on MacOS: Install File::Copy::Recursive perl module cpan install File::Copy::Recursive Include this perl module into @INC (see line 40 on the screenshot below) on easier_uvm_gen.pl.
Because object “seq” was not created prior to starting the #UVM sequencer, questasim crashed horribly with # UVM_INFO @ 0: # uvm_test_top.m_env.m_core_agent Run phase # ** Fatal: (SIGSEGV) Bad handle or reference. # Time: 0 ps Iteration: 50 Process: # /uvm_pkg::uvm_task_phase::execute/#FORK#144(#ublk#43#144)_b6318a1 # Fatal error in Task uvm_pkg/uvm_sequence_base::start # at uvm-1.2/src/seq/uvm_sequence_base.svh line 258 Quick Solution: seq […]
Extraction of tarball from verification academy gunzip -c Uvm_register-2.0.tgz | tar xvzf –