No $time with system task $fatal

On the quest to remove redundant code from my testbenches, $time was among the victims to be dropped from all SV call $fatal.

Now I’m using $realtime instead of $time when writing SVAs.

 

Take the following statement along with its output as example:
$fatal(`ASSERT_LEVEL, "[%m]: Assertion property pp_ahb_readyout_resp failed @ time %0t", $time);

# ** Fatal: [tb_env.ap_ahb[0].readyout_resp]: Assertion property pp_ahb_readyout_resp failed @ time 1410830.00 ns
#    Time: 1410829553 ps Started: 1410496219 ps  Scope: tb_env.ap_ahb[0].readyout_resp File: tb_env.sv Line: 610 Expr: hready_sbus_slv[0]==hreadys

$time is already highlighted by questa’s verbose message.

UVM related command line functions

Some UVM related command line functions on questa:

call’ can be used to call any UVM SV function.

findregisters, fr’ can be used to find HDL registers for a UVM register model.

findsequences, fs’ can be used to find currently active sequences.

find insource’ searches through only compiled code to find the given matching string. The returned text is hyperlinked that can be clicked to go straight to the source code.

START_SEQ and STARTING_SEQ

[START_SEQ] and [STARTING_SEQ] from the transcript got me intrigued: Why UVM’s verbose spits them out?

Screen Shot 2015-01-21 at 12.45.07

[START_SEQ] is due to a sequence start on the sequencer, while [STARTING_SEQ]s are due to start of predefined UVM_REG sequences.

freecellera as a development platform ?

Came across this tweet:

The website says:

Freecellera

Because requiring $7,500 or $25,000 USD a year per member seems counter to the stated goal, “to develop technology standards that are balanced, open, and benefit the worldwide electronics industry.” (emphasis added)

We started a public google group. Feel free to subscribe and contribute to the discussion.

The first thought which came into my mind was the early days of Redhat-Fedora spin-off and how we build Fedora Electronic Lab.

Here, in freecellera’s scenario, the community wants to contribute to UVM without having to pay $$$ for participation. Thus leading to the birth of a development platform for community’s UVM.

Thus far, I noticed that the community is lacking a bit of guidance and understanding of how an opensource community works and how to build it. Later during the week, I’ll share some tips to that mailing list.

TLM in simple english

In blocking tasks, the producer calls the put method through a port.
uvm_blocking_put_port #(type) producer_port;
producer_port.put(item);

The consumer provides an implementation of the put method and declares an export which can be connected to the port of the producer.
uvm_blocking_put_imp #(type, consumer) consumer_export;
function void put (type item);

Connection on the top level component:
m_producer.producer_port.connect (m_consumer.consumer_export);

In diagrams, ports are depicted as square, exports as circle and analysis ports as diamond.

Compared to the put method, the get method has its data flow from the export to the port.

(easier-UVM) and @INC

How to generate UVM testbench code from Doulos‘s easier-uvm script on MacOS:

  • Install File::Copy::Recursive perl module
cpan install File::Copy::Recursive

Screen Shot 2014-10-22 at 12.42.58

  • Include this perl module into @INC (see line 40 on the screenshot below) on easier_uvm_gen.pl.

Screen Shot 2014-10-22 at 12.56.31

(UVM) : fatal error before starting the sequencer

Because object “seq” was not created prior to starting the #UVM sequencer, questasim crashed horribly with

# UVM_INFO @ 0: 
# uvm_test_top.m_env.m_core_agent Run phase 
# ** Fatal: (SIGSEGV) Bad handle or reference.
#    Time: 0 ps  Iteration: 50  Process: 
#  /uvm_pkg::uvm_task_phase::execute/#FORK#144(#ublk#43#144)_b6318a1 
# Fatal error in Task uvm_pkg/uvm_sequence_base::start
# at uvm-1.2/src/seq/uvm_sequence_base.svh line 258

Quick Solution:

seq = core_seq::type_id::create("seq");