Gave my #systemverilog based testbench a quick try with Icarus Verilog from master branch.
Unfortunately, it appears that
interface are not yet supported.
A new Verilator release 3.845 has just been built for Fedora/EPEL repositories, which is an improvement over the previous FEL release of Verilator.
- Fix nested packed arrays and struct, bug600. [Jeremy Bennett] Packed arrays are now represented as a single linear vector in Verilated models. This may affect packed arrays that are public or accessed via the VPI.
- Support wires with data types, bug608. [Ed Lander]
- Support bind, to module names only, bug602. [Ed Lander]
- Support VPI product info, warning calls, etc, bug588. [Rick Porter]
- Support $left, $right and related functions, bug448. [Iztok Jeras]
- Support inside expressions.
- Define SYSTEMVERILOG, SV_COV_START and other IEEE mandated predefines.
- Fix pin width mismatch error, bug595. [Alex Solomatnikov]
- Fix implicit one bit parameter selection, bug603. [Jeremy Bennett]
- Fix signed/unsigned parameter misconversion, bug606. [Jeremy Bennett]
- Fix segfault on multidimensional dotted arrays, bug607. [Jie Xu]
- Fix per-bit array output connection error, bug414. [Jan Egil Ruud]
- Fix package logic var compile error.
- Fix enums with X values.
It will be pushed to the respective Fedora and EPEL testing repositories very soon.
It is a pleasure to announce Free Electronic Lab and open source EDA is the topic of the DVClub Bristol meeting, 20 September 2010, at 11:30-2PM WEST/BST.
The talks will be 12-2PM (7-9AM EDT) via
- web conference
- in Bristol, England (Infineon, Great Western Court, Hunts Ground Road, Stoke Gifford, BS34 8HP)
- Cambridge, England (The ARM office in Cambridge (110 Fulbourn Road, Cambridge, CB1 9NJ)
- and Eindhoven, Netherlands.
The presentations are:
- “Verilator; fast, free, but for me?”, by Wilson Snyder, developer of Verilator.
- “Architecture For Massively Parallel HDL Simulations”, by Rich Porter from Art of Silicon.
- “Free Electronic Lab: Hardware engineering made easy”, by Chitlesh Goorah, Digital Design Engineer, ON Semiconductor and developer of Free Electronic Lab.
- “Processor verification using open source tools and the GCC regression test suite: A case study”, by Dr. Jeremy Bennett, founder and CEO of Embecosm.
We hope to see you (virtually) there. For details and to register, follow these guidelines.
This event is sponsored by ARM, Infineon, the NMI and TVS.
FESCo froze OVM’s entry to Fedora repositories due to lack of opensource tools to interpret OVM. I have sent a long mail describing that the arguments:
- “this means asking user to use proprietary software”
- “does not provide OS user experience”
are useless and they both aren’t true in the case of OVM. ASIC designers also make use of home grown scripts, by the way it is a must.
Mike Mintz wants us to participate in his poll. Some current metrics at 23h11 04/02/09 Brussels with 119 participants:
- OVM : 75
- VMM : 37
- SystemVerilog : 49
- Home Grown: 22
While I suspect that currently most participants are Cadence or MentorGraphics customers, I am rather interested in those home grown verification methodologies. I would like to know more about their features and what they bring in terms of time-effective and interoperability.
I have also reminded the fedora community about FEL’s commitment and that FEL is bridging two different communities with different targets but with opensource software. It is important that lack of information doesn’t refrain progress to be made in such innovative environment Fedora is in.
Fedora Users can download OVM’s rpm from here (source rpm also included).
Cadence and Mentor Graphics have both announced on the same day (4/12/2008)  that Open Verification Methodology is available under the Apache 2 license.
While thousands of verification engineers are already using it, now if OVM gets into Fedora repositories, we will be providing industry-class verification tools for our FEL users. OVM is maintained by Cadence and Mentor Graphics.
Believe me or not, this is one step forward for the Fedora Electronic Users to meet interoperability. However, till now I haven’t seen an opensource systemverilog tool that supports it.
I have just submitted OVM for package review, while hoping to get OVM into Fedora repositories in the upcoming days.