Unlike my other posts in the past decade where I referred to install anything from a rpmbuild, today I just want to get the install done and move on. Prequisites for the yosys installation: $ sudo dnf install clang tcl-devel readline-devel libffi-devel mercurial iverilog Yosys build: $ git clone https://github.com/cliffordwolf/yosys.git $ cd yosys/ $ make …
Category Archives: Design Verification
$realtime in SV assertions
$realtime is the de-facto system function I use when writing SystemVerilog assertions. The limitation of $time lies in its 64-bit integer value. $realtime enables SystemVerilog assertions to be re-used in gate-level simulations. I’m glad that Ben Cohen, the renowned SVA expert, agrees with me on this.
AlexOrr’s first 100 days in formal-land
This weekend, I caught up with a presentation from @AlexOrr of Broadcom in which he talks about his “first 100 days in formal-land”. I wanted to read it for a very long time. After reading the slides offline, I felt that this presentation was worth attending in person. Within those slides, one can feel his …
Reactive UVM slave agent
Went through the Mastering Reactive Slaves in UVM paper, a Technical Committee Award Winner, from SNUG Austin | Friday, September 18, 2015. The topic is indeed attractive and Verilab also presented it at MTV2015.
NO_REG_HW_RESET_TEST
To exclude specific registers from being tested against the predefined UVM sequence uvm_reg_hw_reset_seq: uvm_resource_db#(bit)::set({“REG::”, m_env_cfg.dut_rm.rffe_testctrl_reg.get_full_name(), “*”}, “NO_REG_HW_RESET_TEST”, 1, this);
reg_hw_reset_seq] Response queue overflow
Encountered the following error message today, while using the pre-defined UVM sequence uvm_reg_hw_reset_seq : UVM_ERROR @ 84050000:[uvm_test_top.m_env.m_core_agent.m_core_sequencer.reg_hw_reset_seq] Response queue overflow, response was dropped This occurred because the driver was sending a sequence response to the sequencer via the seq_item_port. The default size of the response queue between the sequence and driver is 8. When the …
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Jasper User Group Conference 2015
Went through the proceedings from Jasper User Group Conference 2015 held on October 7 and 8, 2015 at Cadence San Jose.
Active path during register read access
Stumbled into a data corruption during a register read. The adapter’s bus2reg function is called twice during the transaction. This behaviour is correct as the uvm_sequence_items of both the monitor and the driver (REQ) are broadcasted. But the driver should provide the final data for the adapter to translate. *** register read()’s active path: reg.read() …
First trial with Questa Formal’s AutoCheck
It appears that Questa Formal’s AutoCheck’s documentation isn’t up to date. Aside this, it is indeed simple and quick to setup.
Do not delete Questa’s Excel plugin installer
It caught me by surprise. Questa’s Testplan Tracking Excel plugin installer requires the previously used installer during its update. Unfortunately, it doesn’t even show which version of the installer was previously installed. Thus making hard to first find the correct version of the installed plugin and its installer, prior to the update. Note to self: …
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