In SOC encounter(EDI), the command “all_analysis_views” gives all the views defined in viewDefinitions file. To report active analysis views: report_analysis_views -type active To get all active setup/hold analysis views : all_setup_analysis_views all_hold_analysis_views
Category Archives: tcl
Power aware synthesis
Tips for power aware synthesis with RTL compiler by using dynamic switching activities from a VCD file. The testbench must include the following lines to get all the lower-level signals listed on the VCD $dumpfile (“test.vcd.gz”); $dumpvars (0, testbench.module_tb); Synthesis script set_attr lp_power_analysis_effort medium / read_vcd test.rtl.vcd.gz -vcd_module $design # Build detailed power models for …
Cleaning dead leaves
Before [sourcecode language=”bash”] foreach attr $the_attributes { if { [ set value [ get_attribute $o $attr ] ] != “” && $attr == “ref_name” } { if { $verbose } { echo [ format "%-30s %30s" $name $value ] } lappend _ref_name $value } } [/sourcecode] After [sourcecode language=”bash”] set value [ get_attribute $o "ref_name" …
FEL12: Eclipse for reusable Embedded/VHDL/Verilog IP
The picture shows the respective eclipse-plugins, which will enhance : frontend design autogeneration of documentation and maintenance of professional datasheets Perl/Tcl scripting (Perl modules which featured as from FEL10) version controlled experience for Fedora users. Think Methodology and not random packaging. This is sentence that many people have heard from me. Feeding design methodologies is …
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Choose Tcl/Tk for EDA development
I’ve been a big Synopsys fan since I started using Design Compiler. Using DC with home-brew tcl/tk based scripts which its recent baselines have eased maintainance for EDA engineers. That said, I would recommend Tcl/Tk for the development of opensource (digital) EDA software for the following reasons: new users from the digital asic designers are …