Quick news about the development of VHDL language. It seems that the IEEE P1076 VHDL Standards Working Group has been busy preparing VHDL-2017. It is said that it is almost ready and it is time for the VHDL community to prepare to ballot. Voting on the upcoming standard will be conducted between May and July …
Category Archives: vhdl
Connect VHDL DUT using a record port type
To connect a VHDL DUT which is using VHDL record port type inside a SystemVerilog testbench: First, compile the VHDL package in which the record type definition existed using the -mixedsvvh switch and then import the vhdl package into the SV testbench with import [package name]::*;
FEL12: Eclipse for reusable Embedded/VHDL/Verilog IP
The picture shows the respective eclipse-plugins, which will enhance : frontend design autogeneration of documentation and maintenance of professional datasheets Perl/Tcl scripting (Perl modules which featured as from FEL10) version controlled experience for Fedora users. Think Methodology and not random packaging. This is sentence that many people have heard from me. Feeding design methodologies is …
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JTAG Controller
Today, I spent some time to complete my JTAG Controller VHDL design. I started it a few days before Fedora Electronic Lab 11 release. I was also awaiting the day when someone will talk about a possible merger of Cadence and Magma. Well that news was among my RSS feeds. John Cooley’s email about Apache-DA’s …
FEL: Tidy your VHDL files with a simple Perl script
One of the problems digital designers encounter while working with VHDL is that every designer seems to have his/her coding style. Though many companies enforce some coding styles, some files still entail ad-hoc tabs and spacings. Fedora and EPEL-5 repositories include perl-Hardware-Vhdl-Tidy which helps digital designers from pulling their hairs off while working in a …
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