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Chitlesh Goorah

Chitlesh Goorah

  • ASIC Design & Verification Engineer
    • Introduction to Liberty : CCS, ECSM and NDLM
    • IEEE P1800.2 (UVM)
    • Formal Verification
  • Landscape Photographer
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Tag Archives: productivity

signaltap – signals in red

With signaltap, when the signal is highlighted in red, it is because the signal is invalid after analysis and elaboration. It could be that the signal is not driving anything and got scrapped off. Alternatively, the technology viewer might help to debug.

Posted bychitleshMarch 26, 2014Posted inaltera, fpgaTags: debug, productivity, signaltapLeave a comment on signaltap – signals in red
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