Skip to content
Chitlesh Goorah

Chitlesh Goorah

  • ASIC Design & Verification Engineer
    • Introduction to Liberty : CCS, ECSM and NDLM
    • IEEE P1800.2 (UVM)
    • Formal Verification
  • Landscape Photographer
  • twitter
  • youtube
  • linkedin

Tag Archives: qsys

qsys: signals in interface definition

QSYS does not load signals if the top-level module’s signals are of type std_ulogic.

Posted bychitleshApril 27, 2014Posted inaltera, fpgaTags: qsysLeave a comment on qsys: signals in interface definition
Chitlesh Goorah, Proudly powered by WordPress. Privacy Policy