Power aware synthesis

Tips for power aware synthesis with RTL compiler by using dynamic switching activities from a VCD file. The testbench must include the following linesĀ  to get all the lower-level signals listed on the VCD $dumpfile (“test.vcd.gz”); $dumpvars (0, testbench.module_tb); Synthesis script set_attr lp_power_analysis_effort medium / read_vcd test.rtl.vcd.gz -vcd_module $design # Build detailed power models for …