The intention behind my attendance today at the very first IEEE UVM working group conference call was to follow on what will be dropped, loved or enhanced from the UVM 1.2 base. Thus, I’m keen to see in the future whether the final IEEE P1800.2 spec and sources will be released as a free download …
Continue reading “First meeting of the IEEE P1800.2 Working Group”
On the quest to remove redundant code from my testbenches, $time was among the victims to be dropped from all SV call $fatal. Now I’m using $realtime instead of $time when writing SVAs. Take the following statement along with its output as example: $fatal(`ASSERT_LEVEL, “[%m]: Assertion property pp_ahb_readyout_resp failed @ time %0t”, $time); # …
Because object “seq” was not created prior to starting the #UVM sequencer, questasim crashed horribly with # UVM_INFO @ 0: # uvm_test_top.m_env.m_core_agent Run phase # ** Fatal: (SIGSEGV) Bad handle or reference. # Time: 0 ps Iteration: 50 Process: # /uvm_pkg::uvm_task_phase::execute/#FORK#144(#ublk#43#144)_b6318a1 # Fatal error in Task uvm_pkg/uvm_sequence_base::start # at uvm-1.2/src/seq/uvm_sequence_base.svh line 258 Quick Solution: seq …
Continue reading “(UVM) : fatal error before starting the sequencer”
I see that #UVM 1.2 has a nice +uvm_set_default_sequence plusarg which will turn to be very useful for regression test and portability. e.g +uvm_set_default_sequence=path.to.sequencer, main_phase,seq_type It will allow one to define a sequence from the command line, instead of uvm_config_db #(uvm_object_wrapper)::set(null, “uvm_test_top.my_sequencer.main_phase”,”chosen_sequence”, seq_b::type_id::get());
