Current UVM release I’ve defaulted my projects to: UVM-1.2.

Features I hope to see in the next UVM release:

uvm_reg_hw_reset_seq: Expecting new reset phase in the next release. Till now, reg sequence requires one to reset the DUT prior to its usage.

It is quite a mess currently in terms on how companies interprete UVM-1.2 phases. @Cadence recommends run_phase(). @mentor_graphics’s guideline 5.2 recommends to stay away from reset_phase().

uvm_monitor: Expecting a built-in uvm_analysis_port, like the uvm_driver and uvm_sequencer.
uvm_agent: Expecting a built-in uvm_analysis_port, like the uvm_driver and uvm_sequencer.

New features and improvements

Migration to UVM 1.2 from earlier versions

– Use to port UVM-1.1 based projects to version 1.2
– Manually edit the generated files if needed.
– Perform other manual changes which the scripts does not support.

Migration traps to avoid:

– deprecated features
– backward compatibility and
– compromising simulation speed.

To compile UVM-1.2 with Questa

UVM_HOME=$(shell dirname `which vsim`)/../verilog_src/uvm-1.2/src
VLOG_OPTIONS=-quiet -L mtiUvm -work work
vlib mtiUvm
vmap mtiUvm mtiUvm
vlog +incdir+$(UVM_HOME) $(VLOG_OPTIONS) $(UVM_HOME)/dpi/ +define+QUESTA
vlog +incdir+$(UVM_HOME) $(VLOG_OPTIONS) -work mtiUvm $(UVM_HOME)/
vlog +incdir+$(UVM_HOME) $(VLOG_OPTIONS) -work mtiUvm $(UVM_HOME)/

Useful items for task-based tests

uvm_top.finish_on_completion = 1;

What can we expect from IEEE P1800.2 ?

– Line up of UVM-1.2’s TLM with IEEE1666-2011 (SystemC) ‘s TLM definition.

– Perhaps new features from the 2 sub working groups: Register and TLM

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